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february 2012 doc id 022634 rev 2 1/28 28 LNBH25L lnb supply and control ic with step-up and i2c interface features complete interface between lnb and i2c bus built-in dc-dc converter for single 12 v supply operation and high efficiency (typ. 93% @ 0.5 a) selectable output current limit by external resistor compliant with main satellite receiver output voltage specifications accurate built-in 22 khz tone generator suits widely accepted standards 22 khz tone waveform integrity guaranteed also at no load condition low-drop post regulator and high efficiency step-up pwm with integrated power n-mos allowing low power losses overload and overtemperature internal protection with i2c diagnostic bits lnb short-circuit dynamic protection +/- 4 kv esd tolerant on output power pins applications stb satellite receivers tv satellite receivers pc card satellite receivers description intended for analog and digital satellite receivers/sat-tv and sat-pc cards, the LNBH25L is a monolithic voltage regulator and interface ic, assembled in qfn24 (4x4) specifically designed to provide the 13/18 v power supply and the 22 khz tone signalling to the lnb down-converter in the antenna dish or to the multi-switch box. in this application field, it offers a complete solution with extremely low component count and low power dissipation together with a simple design and i2c standard interfacing. qfn24 (4 x 4 mm) table 1. device summary order code package packaging LNBH25Lpqr qfn24 (4 x 4) tape and reel www.st.com
contents LNBH25L 2/28 doc id 022634 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 diseqc data encoding (dsqin pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 data encoding by external 22 khz tone ttl signal . . . . . . . . . . . . . . . . . . 4 2.3 data encoding by external diseqc? envelope control through the dsqin pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.7 surge protection and tvs diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 power-on i2c interface reset and undervoltage lockout . . . . . . . . . . . . . . . 6 2.9 png: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.10 olf: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7 2.11 otf: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.3 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.5 transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 i2c interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LNBH25L contents doc id 022634 rev 2 3/28 7.4 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
block diagram LNBH25L 4/28 doc id 022634 rev 2 1 block diagram figure 1. block diagram am10460v1 vup sda scl isel addr dsqin isense pwm ctrl pgnd dac drop control tone ctrl diagnostics protections i2c digital core lx voltage reference vcc gnd byp current limit selection vout gate ctrl linear regulator
LNBH25L application information doc id 022634 rev 2 5/28 2 application information this ic has a built-in dc-dc step-up converter that, from a single source (8 v to 16 v), generates the voltages (v up ) that let the integrated ldo post-regulator (generating the 13 v / 18 v lnb output voltages plus the 22 khz diseqc? tone) to work with a minimum dissipated power of 0.5 w typ. @ 500 ma load (the ldo drop voltage is internally kept at v up - v out = 1 v typ.). the ic is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied v cc drops below a fixed threshold (4.7 v typically). the step-up converter soft-start function reduces the inrush current during startup. the ss time is internally fixed at 4ms typ. to switch from 0 to 13 v and 6 ms typ. to switch from 0 to 18 v. 2.1 diseqc data encoding (dsqin pin) the internal 22 khz tone generator is factory trimmed in accordance to diseqc standards, and can be activated in 3 different ways: 1. by an external 22 khz source diseqc data connected to the dsqin logic pin (ttl compatible). in this case the i2c tone control bits must be set: extm = ten = 1. 2. by an external diseqc data envelope source connected to the dsqin logic pin. in this case the i2c tone control bits must be set: extm=0 and ten=1. 3. through the ten i2c bit if a 22 khz presence is requested in continuous mode. in this case the dsqin ttl pin must be pulled high and extm bit set to ?0?. 2.2 data encoding by external 22 khz tone ttl signal in order to improve design flexibility an external tone signal can be input to the dsqin pin by setting the extm bit to ?1?. the dsqin is a logic input pin which activates the 22 khz tone to the v out pin, by using the LNBH25L integrated tone generator. the output tone waveforms are internally controlled by the LNBH25L tone generator in terms of rise/fall time and tone amplitude, while, the external 22 khz signal on the dsqin pin is used to define the frequency and the duty cycle of the output tone. a ttl compatible 22 khz signal is required for the proper control of the dsqin pin function. before sending the ttl signal on the dsqin pin, the extm and ten bits must be previously set to ?1?. as soon as the dsqin internal circuit detects the 22 khz ttl external signal code, the LNBH25L activates the 22 khz tone on the v out output with about 1 s delay from ttl signal activation, and it stops with about 60 s delay after the 22 khz ttl signal on dsqin has expired (refer to figure 2 ). figure 2. tone enable and disable timing (using external waveform) am10426v1 ~ 1 s ~ 60 s dsqin tone output
application information LNBH25L 6/28 doc id 022634 rev 2 2.3 data encoding by external diseqc? envelope control through the dsqin pin if an external diseqc envelope source is available, it is possible to use the internal 22 khz generator activated during the tone transmission by connecting the diseqc envelope source to the dsqin pin. in this case the i2c tone control bits must be set: extm = 0 and ten = 1. in this way, the internal 22 khz signal is superimposed to the v out dc voltage to generate the lnb output 22 khz tone. during the period in which the dsqin is kept high, the internal control circuit activates the 22 khz tone output. the 22 khz tone on the v out pin is activated with about 6 s delay from the dsqin ttl signal rising edge, and it stops with a delay time in the range from 15 s to 60 s after the 22 khz ttl signal on dsqin has expired (refer to figure 3 ). figure 3. tone enable and disable timing (using envelope signal) 2.4 output current limit selection the linear regulator current limit threshold can be set by an external resistor connected to the isel pin. the resistor value defines the output current limit by the equation: equation 1 where rsel is the resistor connected between isel and gnd expressed in k and i max (typ.) is the typical current limit threshold expressed in ma. i max can be set up to 750 ma. 2.5 output voltage selection the linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 bits of an internal data1 register (see section 7.3 and ta bl e 1 3 for exact programmable values). register writing is accessible via the i2c bus. am10427v1 ~ 6 s 15 s ~ 60 s dsqin tone output 111 . 1 max rsel 13915 .) typ ( i =
LNBH25L application information doc id 022634 rev 2 7/28 2.6 diagnostic and protection functions the LNBH25L has 3 diagnostic internal functions provided via the i2c bus, by reading 3 bits on the status1 register (in read mode). all the diagnostic bits are, in normal operation (that is no failure detected), set to low. two diagnostic bits are dedicated to the overtemperature and overload protection status (otf and olf). one bit is dedicated to the input voltage power not good function (png). once the olf (or otf or png) bit has been activated (set to ?1?), it is latched to ?1? until the relevant cause is removed and a new register reading operation is done. 2.7 surge protection and tvs diodes the LNBH25L device is directly connected to the antenna cable in a set-top box. atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. this leads to currents or electromagnetic fields causing high voltage or current transients. transient voltage suppressor (tvs) devices are usually used, as shown in the following schematic, to protect the stb output circuits where the LNBH25L and other devices are electrically connected to the antenna cable. figure 4. surge protection circuit for this purpose we recommend the use of lnbtvsxx surge protection diodes specifically designed by st. the selection of the lnbtvs diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the lnbtvs datasheet for further details). 2.8 power-on i2c interface reset and undervoltage lockout the i2c interface built into the LNBH25L is automatically reset at power-on. as long as the v cc stays below the undervoltage lockout (uvlo) threshold (4.7 v typ.), the interface does not respond to any i2c command and all data register bits are initialized to zeroes, therefore keeping the power blocks disabled. once the v cc rises above 4.8 v typ. the i2c interface becomes operative and the data registers can be configured by the main microprocessor. 2.9 png: input voltage minimum detection when input voltage (v cc pin) is lower than lpd (low power diagnostic) minimum thresholds, the png i2c bit is set to ?1? and the flt pin is set low. refer to ta b l e 1 2 for threshold details.
application information LNBH25L 8/28 doc id 022634 rev 2 2.10 olf: overcurrent and short-circuit protection and diagnostic in order to reduce the total power dissipation during an overload or a short-circuit condition, the device is provided with a dynamic short-circuit protection. it is possible to set the short- circuit current protection either statically (simple current clamp) or dynamically by the pcl bit of the i2c data3 register. when the pcl (pulsed current limiting) bit is set to low, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for a t on time of 90 ms, after which the output is set in shutdown for a t off time of typically 900 ms. simultaneously, the diagnostic olf i2c bit of the system register is set to ?1?. after this time has elapsed, the output is resumed for a time t on . at the end of t on , if the overload is still detected, the protection circuit cycles again through t off and t on . at the end of a full t on in which no overload is detected, normal operation is resumed and the olf diagnostic bit is reset to low after a register reading is done. typical t on + t off time is 990 ms and an internal timer determines it. this dynamic operation can greatly reduce the power dissipation in a short-circuit condition, still ensuring excellent power-on startup in most conditions. however, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. this can be solved by initiating any power startup in static mode (pcl=1) and then switching to the dynamic mode (pcl=0) after a chosen amount of time depending on the output capacitance. also in static mode, the diagnostic olf bit goes to ?1? when the current clamp limit is reached and returns low when the overload condition is cleared and a register reading is done. after the overload condition is removed, normal operation can be resumed in two ways, according to the olr i2c bit on the data4 register. if olr=1, all vsel 1..4 bits are reset to ?0? and lnb output (v out pin) is disabled. to re- enable the output stage, the vsel bits must be set again by the microprocessor, and the olf bit is reset to ?0? after a register reading operation. if olr=0, output is automatically re-enabled as soon as the overload condition is removed, and the olf bit is reset to ?0? after a register reading operation. 2.11 otf: thermal protection and diagnostic the LNBH25L is also protected against overheating: when the junction temperature exceeds 150 c (typ.), the step-up converter and the linear regulator are shut off, the diagnostic otf bit in the status1 register is set to ?1?. after the overtemperature condition is removed, normal operation can be resumed in two ways, according to the therm i2c bit on the data4 register. if therm=1, all vsel 1..4 bits are reset to ?0? and lnb output (v out pin) is disabled. to re- enable the output stage, the vsel bits must be set again by the microprocessor, while the otf bit is reset to ?0? after a register reading operation. if therm=0, output is automatically re-enabled as soon as the overtemperature condition is removed, while the otf bit is reset to ?0? after a register reading operation.
LNBH25L pin configuration doc id 022634 rev 2 9/28 3 pin configuration figure 5. pin connections (top view) am10461v1 gnd gnd nc dsqin vup vcc pgnd gnd nc lx sda isel nc nc gnd nc nc vout nc vbyp gnd addr nc scl 1 2 3 4 5 6 18 17 16 15 14 13 7 8 9 12 11 10 19 20 21 22 23 24 LNBH25L table 2. pin description pin n symbol name pin function 3 lx n-mos drain integrated n-channel power mosfet drain. 4 p-gnd power ground dc-dc converter power ground. to be connected directly to the epad. 6 addr address setting two i2c bus addresses available by setting the address pin level voltage. see ta b l e 1 5 . 7 scl serial clock clock from i2c bus. 8 sda serial data bi-directional data from/to the i2c bus. 9 isel current selection the resistor ?rsel? connected between isel and gnd defines the linear regulator current limit threshold. refer to section 2.4 . 2,15, 18, 19, 23 gnd analog ground analog circuits ground. to be connected directly to the epad. 16 byp bypass capacitor needed for internal pre-regulator filtering. the byp pin is intended only to connect an external ceramic capacitor. any connection of this pin to external current or voltage sources may cause permanent damage to the device. 17 v cc supply input 8 to 16 v ic dc-dc power supply. 20 v out lnb output port output of the integrated very low drop linear regulator. see ta bl e 1 3 for voltage selection and description. 21 v up step-up voltage input of the linear post-regulator. the voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor.
pin configuration LNBH25L 10/28 doc id 022634 rev 2 pin n symbol name pin function 22 dsqin dsqin for diseqc envelope input or external 22 khz ttl input it can be used as diseqc envelope input or external 22 khz ttl input depending on the extm i2c bit setting as follows: extm=0, ten=1: it accepts the diseqc envelope code from the main microcontroller. the LNBH25L uses this code to modulate the internally generated 22 khz carrier. extm=ten=1: it accepts external 22 khz logic signals which activate the 22 khz tone output (refer to section 2.3 ). pull up high if the tone output is activated only by the ten i2c bit. epad epad exposed pad to be connected with power grounds and to the ground layer through vias to dissipate the heat. 1, 5, 10, 11, 12, 13, 14, 24 n.c. not internally connected not internally connected pins. these pins can be connected to gnd to improve thermal performances. table 2. pin description (continued)
LNBH25L maximum ratings doc id 022634 rev 2 11/28 4 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to the network ground terminal. table 3. absolute maximum ratings symbol parameter value unit v cc dc power supply input voltage pins -0.3 to 20 v v up dc input voltage -0.3 to 40 v i out output current internally limited ma v out dc output pin voltage -0.3 to 40 v v i logic input pins voltage (sda, scl, dsqin, addr pins) -0.3 to 7 v lx lx input voltage -0.3 to 30 v v byp internal reference pin voltage -0.3 to 4.6 v isel current selection pin voltage -0.3 to 3.5 v t stg storage temperature range -50 to 150 c t j operating junction temperature range -25 to 125 c esd esd rating with human body model (hbm) all pins, unless power output pins 2kv esd rating with human body model (hbm) for power output pins 4 table 4. thermal data symbol parameter value unit r thjc thermal resistance junction-case 2 c/w r thja thermal resistance junction-ambient with device soldered on 2s2p 4- layer pcb provided with thermal vias below exposed pad. 40 c/w
typical application circuits LNBH25L 12/28 doc id 022634 rev 2 5 typical application circuits figure 6. diseqc 1.x application circuit table 5. typical application circuit bill of material component notes r1 (rsel) smd resistor. refer to ta b l e 1 2 and isel pin description in ta bl e 2 c1, c2 > 25 v electrolytic capacitor, 100 f is suitable. c3 from 470 nf to 2.2 f ceramic capacitor. higher values allow lower dc-dc noise. c5 from 100 nf to 220 nf ceramic capacitor. higher values allow lower dc-dc noise. c4, c7 220 nf ceramic capacitors. d1 stps130a or similar schottky diode. d3 bat54, bat43, 1n5818, or any low power schottky diode with i f (av) > 0.2 a, v rrm > 25 v, v f < 0.5 v. to be placed as close as possible to v out pin. d2 1n4001-07, s1a-s1m, or any similar general purpose rectifier. l1 10 h inductor with i sat > i peak where i peak is the boost converter peak current. am10462v1 l1 c3 vin 12v to lnb lx vup vout addr c4 LNBH25L { i 2 c bus sda scl p-gnd a-gnd d1 c5 isel r1 (rsel) byp c7 dsqin c2 c1 vcc d2 diseqc envelope ttl or diseqc 22khz ttl d3 21 3 17 16 9 8 7 4 15 6 22 20
LNBH25L i2c bus interface doc id 022634 rev 2 13/28 6 i2c bus interface data transmission from the main microprocessor to the LNBH25L and vice versa takes place through the 2-wire i2c bus interface, consisting of the 2-line sda and scl (pull-up resistors to positive supply voltage must be externally connected). 6.1 data validity as shown in figure 7 , the data on the sda line must be stable during the high semi-period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 6.2 start and stop condition as shown in figure 8 , a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. a stop condition must be sent before each start condition. 6.3 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 6.4 acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse (see figure 9 ). the peripheral (LNBH25L) that acknowledges must pull down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral which has been addressed must generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. the LNBH25L does not generate an acknowledge if the v cc supply is below the undervoltage lockout threshold (4.7 v typ.). 6.5 transmission without acknowledge to avoid detection of the LNBH25L acknowledges, the microprocessor can use a simpler transmission: it simply waits one clock cycle without checking the slave acknowledging, and sends the new data. this approach is of course less protected from misworking and decreases the noise immunity.
i2c bus interface LNBH25L 14/28 doc id 022634 rev 2 figure 7. data validity on the i2c bus figure 8. timing diagram of i2c bus figure 9. acknowledge on the i2c bus
LNBH25L i2c interface protocol doc id 022634 rev 2 15/28 7 i2c interface protocol 7.1 write mode transmission the LNBH25L interface protocol is made up of: a start condition (s) a chip address byte with the lsb bit r/w = 0 a register address (internal address of the first register to be accessed) a sequence of data (byte to write in the addressed internal register + acknowledge) the following bytes, if any, to be written in successive internal registers a stop condition (p). the transfer lasts until a stop bit is encountered the LNBH25L, as slave, acknowledges every byte transfer. figure 10. example of writing procedure starting with first data address 0x2 (a) ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the values to select the chip address (see ta bl e 1 5 for pin selection) and to select the register address (see ta b l e 6 to ta b l e 1 1 ). a. the writing procedure can start from any register address by simply setting the x values in the register address byte (after the chip address). it can be also stopped from the master by sending a stop condition after any acknowledge bit. am1046 3 v1 s 000100x r/w = 0 ack 00000xxx ack n/a n/a n/a n/a vsel4 vsel3 vsel2 vsel1 ack msb lsb chip address msb lsb register address n/a n/a n/a n/a n/a extm n/a ten ack n/a n/a n/a n/a n/a pcl n/a n/a ack n/a therm n/a n/a n/a n/a n/a ack p msb lsb msb lsb msb lsb msb lsb data 1 add=0x2 data 2 add=0x3 data 3 add=0x4 data 4 add=0x5 olr
i2c interface protocol LNBH25L 16/28 doc id 022634 rev 2 7.2 read mode transmission in read mode the bytes sequence must be as follows: a start condition (s) a chip address byte with the lsb bit r/w=0 the register address byte of the internal first register to be accessed a stop condition (p) a new master transmission with the chip address byte and the lsb bit r/w=1 after the acknowledge the LNBH25L starts to send the addressed register content. as long as the master keeps the acknowledge low, the LNBH25L transmits the next address register byte content. the transmission is terminated when the master sets the acknowledge high with a following stop bit. figure 11. example of reading procedure starting with first status address 0x0 (b) ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the values to select the chip address (see ta bl e 1 5 for pin selection) and to select the register address (see ta b l e 6 to ta b l e 1 1 ). b. the reading procedure can star t from any register address (status 1, 2 or data1..4) by simply setting the x values in the register address byte (after the first chip address in the above figure). it can be also stopped from the master by sending a stop condition after any acknowledge bit. am10464v1 s 000100x r/w = 0 ack 00000xxx ack p n/a n/a n/a n/a vsel4 vsel3 vsel2 vsel1 ack n/a n/a n/a n/a n/a extm n/a ten ack n/a n/a n/a n/a n/a pcl n/a n/a ack n/a therm n/a n/a olr n/a n/a n/a ack p n/a n/a n/a n/a n/a n/a n/a n/a ack png otf n/a n/a n/a n/a n/a olf ack msb lsb data 1 add=0x2 msb lsb data 2 add=0x3 msb lsb data 3 add=0x4 msb lsb data 4 add=0x5 msb lsb status 2 add=0x1 msb lsb status 1 add=0x0 s000100x r/w = 1 ack msb lsb chip address msb lsb register address msb lsb chip address
LNBH25L i2c interface protocol doc id 022634 rev 2 17/28 7.3 data registers the data 1..4 registers can be addressed both in write and read mode. in read mode they return the last writing byte status received in the previous write transmission. the following tables provide the register address values of data 1..4 and a function description of each bit. n/a = reserved bit. all bits reset to ?0? at power-on. n/a = reserved bit. all bits reset to ?0? at power-on. table 6. data 1 (read/write register. register address = 0x2) bit name value description bit 0 (lsb) vsel1 0/1 output voltage selection bits. (refer to ta bl e 1 3 ) bit 1 vsel2 0/1 bit 2 vsel3 0/1 bit 3 vsel4 0/1 bit 4 n/a 0 reserved. keep to ?0? bit 5 n/a 0 reserved. keep to ?0? bit 6 n/a 0 reserved. keep to ?0? bit 7 (msb) n/a 0 reserved. keep to ?0? table 7. data 2 (read/write register. register address = 0x3) bit name value description bit 0 (lsb) ten 1 22 khz tone enabled. tone output controlled by the dsqin pin 0 22 khz tone output disabled bit 1 n/a 0 reserved. keep to ?0? bit 2 extm 1 dsqin input pin is set to receive external 22 khz ttl signal source 0 dsqin input pin is set to receive external diseqc envelope ttl signal bit 3 n/a 0 reserved. keep to ?0? bit 4 n/a 0 reserved. keep to ?0? bit 5 n/a 0 reserved. keep to ?0? bit 6 n/a 0 reserved. keep to ?0? bit 7 (msb) n/a 0 reserved. keep to ?0?
i2c interface protocol LNBH25L 18/28 doc id 022634 rev 2 n/a = reserved bit. all bits reset to ?0? at power-on. n/a = reserved bit. all bits reset to ?0? at power-on. table 8. data 3 (read/write register. register address = 0x4) bit name value description bit 0 (lsb) n/a 0 reserved. keep to ?0? bit 1 n/a 0 reserved. keep to ?0? bit 2 pcl 1 pulsed (dynamic) lnb output current limiting is deactivated 0 pulsed (dynamic) lnb output current limiting is activated bit 3 n/a 0 reserved. keep to ?0? bit 4 n/a 0 reserved. keep to ?0? bit 5 n/a 0 reserved. keep to ?0? bit 6 n/a 0 reserved. keep to ?0? bit 7 (msb) n/a 0 reserved. keep to ?0? table 9. data 4 (read/write register. register address = 0x5) bit name value description bit 0 (lsb) n/a 0 reserved. keep to ?0? bit 1 n/a 0 reserved. keep to ?0? bit 2 n/a 0 reserved. keep to ?0? bit 3 olr 1 in case of overload protection activation (olf=1), all vsel 1..4 bits are reset to ?0? and lnb output (v out pin) is disabled. the vsel bits must be set again by the master after the overcurrent condition is removed (olf=0). 0 in case of overload protection activation (olf=1) the lnb output (v out pin) is automatically enabled as soon as the overload condition is removed (olf=0) with the previous vsel bits setting. bit 4 n/a 0 reserved. keep to ?0? bit 5 n/a 0 reserved. keep to ?0? bit 6 therm 1 if thermal protection is activated (otf=1), all vsel 1..4 bits are reset to ?0? and lnb output (v out pin) is disabled. the vsel bits must be set again by the master after the overtemperature condition is removed (otf=0). 0 in case of thermal protection activation (otf=1) the lnb output (v out pin) is automatically enabled as soon as the overtemperature condition is removed (otf=0) with the previous vsel bits setting. bit 7 (msb) n/a 0 reserved. keep to ?0?
LNBH25L i2c interface protocol doc id 022634 rev 2 19/28 7.4 status registers the status 1, 2 registers can be addressed only in read mode and provide the diagnostic functions described in the following tables. n/a = reserved bit. all bits reset to ?0? at power-on. n/a = reserved bit. all bits reset to ?0? at power-on. table 10. status 1 (read register. register address = 0x0) bit name value description bit 0 (lsb) olf 1 v out pin overload protection has been triggered (i out > i max ). refer to ta bl e 8 for the overload operation settings (pcl bit). 0 no overload protection has been triggered to the v out pin (i out < i max ). bit 1 n/a - reserved bit 2 n/a - reserved bit 3 n/a - reserved bit 4 n/a - reserved bit 5 n/a - reserved bit 6 otf 1 junction overtemperature is detected, t j > 150 c. see also the therm bit setting in ta b l e 9 . 0 junction overtemperature not detected, t j < 135 c. t j is below thermal protection threshold. bit 7 (msb) png 1 input voltage (v cc pin) lower than lpd minimum thresholds. refer to ta b l e 1 2 . 0 input voltage (v cc pin) higher than lpd thresholds. refer to ta bl e 1 2 . table 11. status 2 (read register. register address = 0x1) bit name value description bit 0 (lsb) n/a - reserved bit 1 n/a - reserved bit 2 n/a - reserved bit 3 n/a - reserved bit 4 n/a - reserved bit 5 n/a - reserved bit 6 n/a - reserved bit 7 (msb) n/a - reserved
electrical characteristics LNBH25L 20/28 doc id 022634 rev 2 8 electrical characteristics refer to section 5 , t j from 0 to 85 c, all data 1..4 register bits set to 0 unless vsel1 = 1, rsel = 16.2 k , dsqin = low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = v out pin voltage. see software description section for i2c access to the system register ( section 6 and section 7 ). . table 12. electrical characteristics symbol parameter test conditions min. typ. max. unit v in supply voltage (1) 81216v i in supply current i out =0 ma 6 ma 22 khz tone enabled (ten=1, dsqin=high), i out =0 ma 10 vsel1=vsel2=vsel3=vsel4=0 1 v out output voltage total accuracy valid at any v out selected level -3.5 +3.5 % v out line regulation v in =8 to 16 v 40 mv v out load regulation i out from 50 to 500 ma 75 100 i max output current limiting thresholds rsel = 16.2 k rsel = 22 k 500 750 ma 350 550 i sc output short-circuit current rsel= 16.2 k 350 ma ss soft-start time v out from 0 to 13 v 4 ms ss soft-start time v out from 0 to 18 v 6 ms t13-18 soft transition rise time v out from 13v to 18 v 1.5 ms t18-13 soft transition fall time v out from 18v to 13 v 1.5 ms t off dynamic overload protection off time pcl=0, output shorted 900 ms t on dynamic overload protection on time pcl=0, output shorted t off /10 a tone tone amplitude dsqin=high, extm=0, ten=1 i out from 0 to 500 ma c bus from 0 to 750 nf 0.55 0.675 0.8 v pp f tone tone frequency dsqin=high, extm=0, ten=1 20 22 24 khz d tone tone duty cycle 43 50 57 % t r , t f tone rise or fall time (2) 5815s eff dc/dc dc-dc converter efficiency i out =500ma 93 % f sw dc-dc converter switching frequency 440 khz uvlo undervoltage lockout thresholds uvlo threshold rising 4.8 v uvlo threshold falling 4.7 v lp low power diagnostic (lpd) thresholds v lp threshold rising 7.2 v v lp threshold falling 6.7
LNBH25L electrical characteristics doc id 022634 rev 2 21/28 symbol parameter test conditions min. typ. max. unit v il dsqin, pin logic low 0.8 v v ih dsqin, pin logic high 2 v i ih dsqin, pin input current v ih =5 v 15 a i obk output backward current all vselx=0, v obk =30 v -3 - 6ma i sink output low-side sink current v out forced at v out_nom +0.1 v 70 ma i sink_time- out low-side sink current timeout v out forced at v out_nom +0.1 v 10 ms i rev max. reverse current v out forced at v out_nom +0.1 v, after i sink_time-out is elapsed 2ma t shdn thermal shutdown threshold 150 c t shdn thermal shutdown hysteresis 15 c 1. in applications where (v cc -v out ) >1.3 v, the increased power dissipation inside the integrated ldo must be taken into account in the application thermal management design. 2. guaranteed by design. table 12. electrical characteristics (continued) table 13. output voltage selection table (data1 register, write mode) vsel4 vsel3 vsel2 vsel1 v out min. v out pin voltage v out max. function 0000 0.000 v out disabled. LNBH25L set in standby 000112.54513.00013.455 001012.86713.33313.800 001113.18813.66714.145 010013.5114.00014.490 100017.51518.15018.785 100117.83618.48319.130 101018.15818.81719.475 101118.4819.15019.820
electrical characteristics LNBH25L 22/28 doc id 022634 rev 2 t j from 0 to 85 c, v i = 12 v. t j from 0 to 85 c, v i = 12 v. table 14. i2c electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage sda, scl 0.8 v v ih high level input voltage sda, scl 2 v i in input current sda, scl, v in = 0.4 to 4.5 v -10 10 a v ol low level output voltage (1) sda (open drain), i ol = 6 ma 0.6 v f max maximum clock frequency scl 400 khz 1. guaranteed by design. table 15. address pin characteristics symbol parameter test condition min. typ. max. unit v addr-1 ?0001000(r/w)? address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 00.8v v addr-2 ?0001001(r/w)? address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 25v
LNBH25L package mechanical data doc id 022634 rev 2 23/28 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 16. qfn24l (4 x 4 mm) mechanical data dim. (mm) min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 3.90 4.00 4.10 d2 2.55 2.70 2.80 e 3.90 4.00 4.10 e2 2.55 2.70 2.80 e 0.45 0.50 0.55 l 0.25 0.35 0.45
package mechanical data LNBH25L 24/28 doc id 022634 rev 2 figure 12. qfn24l (4 x 4 mm) package dimensions 7596209_d
LNBH25L package mechanical data doc id 022634 rev 2 25/28 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 4. 3 5 0.171 bo 4. 3 5 0.171 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (4x4) mechanical data
package mechanical data LNBH25L 26/28 doc id 022634 rev 2 figure 13. qfn24l (4 x 4) footprint recommended data (mm.)
LNBH25L revision history doc id 022634 rev 2 27/28 10 revision history table 17. document revision history date revision changes 09-jan-2012 1 initial release. 15-feb-2012 2 modified: d1 and d3 table 5 on page 12 .
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